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gitlab.telecom-paris.fr / sen / dev-projects / sv_sim_uart

SystemVerilog simulation environment for an UART

JSON API: https://repos.data.code.gouv.fr/api/v1/hosts/gitlab.telecom-paris.fr/repositories/sen%2Fdev-projects%2Fsv_sim_uart

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License: None
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Dependencies parsed at: Pending

Created at: over 5 years ago
Updated at: about 5 years ago
Last synced at: 7 months ago

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